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integrated circuit systems, inc. ics9248-99 0314c?09/18/03 block diagram recommended application: 810/810e style chipset output features: 2- cpus @2.5v @ 150mhz (up to 200mhz. achievable through i 2 c) 9 - sdram @ 3.3v @ 150mhz (up to 200mhz. achievable through i 2 c) 8 - pciclk @ 3.3v 1 - ioapic @ 2.5v, 2 - 3v66mhz @ 3.3v 2- 48mhz, @ 3.3v fixed. 1- 24/48mhz, @ 3.3v 1- ref @3.3v, 14.318mhz. features: up to 200.4mhz frequency support support fs0-fs3 trapping status bit for i 2 c read back. support power management: power down mode form i 2 c programming. spread spectrum for emi control ( 0.25% center). fs0, fs1, fs2, fs3 must have a internal 120k pull- down to gnd. uses external 14.318mhz crystal skew specifications: cpu ? cpu: <175ps sdram - sdram: < 250ps 3v66 ? 3v66: <175ps pci ? pci: <500ps for group skew specifications, please refer to group timing relationship table. functionality - s f 3 - s f 2 - s f 1 0 s f u p c ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p * 6 6 v 3 ( ) 2 / 1 ) z h m ( c i p a o i * i c p ( ) 2 / 1 ) z h m ( c i p a o i ) i c p ( ) z h m ( 000 0 3 3 . 5 70 0 . 3 1 13 3 . 5 77 6 . 7 33 8 . 8 17 6 . 7 3 000 1 0 0 . 5 2 10 0 . 5 2 13 3 . 3 87 6 . 1 43 8 . 0 27 6 . 1 4 0010 0 0 . 9 2 10 0 . 9 2 10 0 . 6 80 0 . 3 40 5 . 1 20 0 . 3 4 001 1 9 2 . 0 5 10 0 . 3 1 13 3 . 5 77 6 . 7 33 8 . 8 17 6 . 7 3 0100 0 0 . 0 5 10 0 . 0 5 10 0 . 0 0 10 0 . 0 50 0 . 5 20 0 . 0 5 010 1 0 0 . 2 1 10 0 . 2 1 17 6 . 4 73 3 . 7 37 6 . 8 13 3 . 7 3 0110 0 0 . 5 4 10 0 . 5 4 17 6 . 6 93 3 . 8 47 1 . 4 23 3 . 8 4 0111 4 6 . 3 4 10 0 . 8 0 10 0 . 2 70 0 . 6 30 0 . 8 10 0 . 6 3 100 0 0 3 . 8 60 5 . 2 0 13 3 . 8 67 1 . 4 38 0 . 7 17 1 . 4 3 100 1 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3 10 1 0 0 0 . 8 3 10 0 . 8 3 10 0 . 2 90 0 . 6 40 0 . 3 20 0 . 6 4 10 1 1 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3 110 0 7 6 . 6 60 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 110 1 0 0 . 0 0 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 1110 0 6 . 3 3 10 6 . 3 3 17 0 . 9 83 5 . 4 47 2 . 2 23 5 . 4 4 111 1 3 3 . 3 3 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 pin configuration 48-pin 300mil ssop * these inputs have a 120k pull down to gnd. 1 these are double strength. frequency generator & integrated buffers for celeron & p ii / iii ?
2 ics9248-99 0314c?09/18/03 general description pin configuration the ics9248-99 is the single chip clock solution for desktop designs using 810/810/e style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248- 99 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. power groups gndref, vddref = ref1, x1, x2 gndpci , vddpci = pciclk [7:0] gndsdr, vddsdr = sdram [8:0] gndcor, vddcor = supply for pll core gnd3v66 , vdd3v66 = 3v66 vdd48 = 48mhz, 24_48mhz, vddlapic = ioapic gndlcpu , vddlcpu = cpuclk [1:0] pin number pin name type description ref1 out 14.318 mhz reference clock. fs3 in frequency select pin. 2, 6, 16, 24, 27, 34, 42 vdd pwr 3.3v power supply for sdram output buffers, pci output buffers, reference out p ut buffers and 48mhz out p ut 3 x1 in crystal input,nominally 14.318mhz. 4 x2 out crystal output, nominally 14.318mhz. 5, 9, 13, 20, 26, 30, 38 gnd pwr ground pin for 3v outputs. 8, 7 3v66 [1:0] out 3.3v clock outputs fs0 in frequency select pin. pciclk0 out pci clock output. fs1 in frequency select pin. pciclk1 out pci clock output. fs2 in frequency select pin. pciclk2 out pci clock output. 19, 18, 17, 15, 14 pciclk [7:3] out pci clock outputs. 21, 22 48mhz out 48mhz output clocks sel24_48# in select pin for enabling 24mhz or 48mhz h=24mhz l=48mhz 24_48mhz out clock output for super i/o/usb 25 sdata in data input for i2c serial input, 5v tolerant input 28 sclk in clock input of i2c input, 5v tolerant input 29 pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are sto pp ed. the latenc y of the p ower down will not be g reater than 3ms. 31, 32, 33, 35, 36, 37, 39, 40, 41 sdram [8:0] out sdram clock outputs 43 gndlcpu pwr ground pin for the cpu clocks. 44, 45 cpuclk [1:0] out cpu clock outputs. 46 vddlcpu pwr power pin for the cpuclks. 2.5v 47 ioapic out 2.5v clock output. 48 vddlapic pwr power pin for the ioapic. 2.5v 23 1 11 12 10
3 ics9248-99 0314c?09/18/03 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
4 ics9248-99 0314c?09/18/03 byte4: functionality and frequency select register (default = 0) serial configuration command bitmap note 1 : default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. 1) the ioapic frequency change from ioapic=pciclk/2 to ioapic=pciclk is controlled by ioapc_freq control in i 2 c byte 3 bit 1 2) the i 2 c readback of the power up default indicate the revision id in bits 2, 7:4 i 2 c is a trademark of philips corporation t i bn o i t p i r c s e dd w p , 2 t i b 4 : 7 t i b ) 4 : 7 , 2 ( t i b k l c u p c ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p z h m ( c i p a o i ) z h m ( 1 1 0 0 0 1 e t o n 2 / i c p =i c p = 00000 3 3 . 5 70 0 . 3 1 13 3 . 5 77 6 . 7 33 8 . 8 17 6 . 7 3 00001 0 0 . 5 2 10 0 . 5 2 13 3 . 3 87 6 . 1 43 8 . 0 27 6 . 1 4 00010 0 0 . 9 2 10 0 . 9 2 10 0 . 6 80 0 . 3 40 5 . 1 20 0 . 3 4 00011 9 2 . 0 5 10 0 . 3 1 13 3 . 5 77 6 . 7 33 8 . 8 17 6 . 7 3 00100 0 0 . 0 5 10 0 . 0 5 10 0 . 0 0 10 0 . 0 50 0 . 5 20 0 . 0 5 00101 0 0 . 2 1 10 0 . 2 1 17 6 . 4 73 3 . 7 37 6 . 8 13 3 . 7 3 00110 0 0 . 5 4 10 0 . 5 4 17 6 . 6 93 3 . 8 47 1 . 4 23 3 . 8 4 00111 4 6 . 3 4 10 0 . 8 0 10 0 . 2 70 0 . 6 30 0 . 8 10 0 . 6 3 01000 0 3 . 8 60 5 . 2 0 13 3 . 8 67 1 . 4 38 0 . 7 17 1 . 4 3 01001 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3 01010 0 0 . 8 3 10 0 . 8 3 10 0 . 2 90 0 . 6 40 0 . 3 20 0 . 6 4 01011 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3 01100 7 6 . 6 60 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 01101 0 0 . 0 0 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 01110 0 6 . 3 3 10 6 . 3 3 17 0 . 9 83 5 . 4 47 2 . 2 23 5 . 4 4 01111 3 3 . 3 3 10 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 13 3 . 3 3 10000 4 9 . 6 5 10 0 . 8 1 17 6 . 8 73 3 . 9 37 6 . 9 13 3 . 9 3 10001 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 20 0 . 0 4 100 10 0 3 . 6 4 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 17 6 . 6 3 100 11 0 0 . 7 2 15 2 . 5 90 5 . 3 65 7 . 1 38 8 . 5 15 7 . 1 3 10 100 0 0 . 7 2 10 0 . 7 2 17 6 . 4 83 3 . 2 47 1 . 1 23 3 . 2 4 10 10 1 0 0 . 1 2 10 0 . 1 2 17 6 . 0 83 3 . 0 47 1 . 0 23 3 . 0 4 10 110 0 0 . 7 1 10 0 . 7 1 10 0 . 8 70 0 . 9 30 5 . 9 10 0 . 9 3 10111 0 0 . 4 1 10 0 . 4 1 10 0 . 6 70 0 . 8 30 0 . 9 10 0 . 8 3 11000 0 0 . 0 80 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 20 0 . 0 4 11001 0 0 . 8 70 0 . 7 1 10 0 . 8 70 0 . 9 30 5 . 9 10 0 . 9 3 11010 0 0 . 0 0 20 0 . 0 0 23 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 6 11011 0 0 . 0 8 10 0 . 0 8 10 0 . 0 2 10 0 . 0 60 0 . 0 30 0 . 0 6 11100 0 0 . 6 6 10 0 . 6 6 17 6 . 0 1 13 3 . 5 57 6 . 7 23 3 . 5 5 11101 0 0 . 0 1 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 17 6 . 6 3 11110 0 0 . 7 0 10 0 . 7 0 13 3 . 1 77 6 . 5 33 8 . 7 17 6 . 5 3 11111 0 0 . 0 90 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 10 0 . 0 3 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 2 . 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
5 ics9248-99 0314c?09/18/03 byte 0: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b3 21 z h m 8 4 / 4 2 1 t i b2 2 , 1 21 z h m 8 4 0 t i b-0 d e v r e s e r notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inferted logic load of the input frequency select pin conditions. byte 3: reserved , active/inactive register (1= enable, 0 = disable) byte 5: peripheral , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-0 d e v r e s e r 1 t i b-0 d e v r e s e r 0 t i b-0 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b9 11 7 k l c i c p 6 t i b8 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b5 11 4 k l c i c p 3 t i b4 11 3 k l c i c p 2 t i b2 11 2 k l c i c p 1 t i b1 11 1 k l c i c p 0 t i b0 11 0 k l c i c p byte 1: sdram, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b2 31 7 m a r d s 6 t i b3 31 6 m a r d s 5 t i b5 31 5 m a r d s 4 t i b6 31 4 m a r d s 3 t i b7 31 3 m a r d s 2 t i b9 31 2 m a r d s 1 t i b0 41 1 m a r d s 0 t i b1 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-x# 2 s f 5 t i b-x# 1 s f 4 t i b-x# 0 s f 3 t i b7 41 c i p a o i 2 t i b-x # ) # 8 4 _ 4 2 l e s ( 1 t i b-1 c i p a o i _ q e r f 2 / k l c i c p = c i p a o i > = 1 = > = 0 = c i p a o i _ q e r f k l c i c p = c i p a o i 0 t i b-x# 3 s f
6 ics9248-99 0314c?09/18/03 shared pin operation - input/output pins fig. 1 the i/o pins designated by (input/output) on the ics9248- 99 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
7 ics9248-99 0314c?09/18/03 fig. 2a fig. 2b
8 ics9248-99 0314c?09/18/03 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-99 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. p u o r gz h m 6 6 u p cz h m 0 0 1 u p cz h m 3 3 1 u p c t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 i c p o t i c ps n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / n group timing relationship table
9 ics9248-99 0314c?09/18/03 absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3v +5%, v ddl =2.5 v+-5%(unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2 v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd = 0 v; inputs with no pull-up resistors -5 5 ma input low current i il1 v in = 0 v; inputs with pull-up resistors -5 2 ma input low current i il2 v in -200 -100 ma operating supply current i dd3.3op c l = 0 pf; select @ 66m 60 100 ma power down supply current i dd3.3pd c l = 0 pf; with input address to v dd or gnd 400 600 a input frequency f i 14.32 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x 1 & x 2 pins 27 45 pf transition time 1 t trans to 1 st crossing of target freq. 3ms settling time 1 t s from 1 st crossing to 1% target freq. 3ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay(all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay input capacitance 1 v dd = 3.3 v;
10 ics9248-99 0314c?09/18/03 electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2b v o = v d d *(0.5) 13.5 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @min= 1.0v -27 v oh @max= 2.375v -27 v ol @min= 1.2v 27 v ol @max= 0.3v 30 rise time t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time t f2b v oh = 0.4 v, v ol = 2.0 v 0.4 1.1 1.6 ns d t2b v t = 1.25 v cpumhz < 133 45 49 55 % d t2b v t = 1.25 v cpumhz =133 40 44 50 % d t2b v t = 1.25 v cpumhz >133 45 51 55 % skew t sk2b v t = 1.25 v 30 175 ps t j c y c-c y c v t = 1.25 v f cpu = f sdram 120 250 ps t jcyc-cyc v t = 1.25 v cpu/sdram=133/100 330 350 ps 1 guaranteed by design, not 100% tested in production. jitter duty cycle ma ma i ol2b i oh2b output high current output low current electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max= 0.4 38 ma rise time t r1 v ol = 0.4 v, v oh = 2.4 0.4 1.4 1.9 ns fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.3 1.6 ns duty cycle d t1 v t = 1.5 v 45 48 55 % skew t sk1 v t = 1.5 v 30 175 ps jitter t jcyc-cyc v t = 1.5 v 270 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 i ol1 output low current
11 ics9248-99 0314c?09/18/03 electrical characteristics - ioapic t a = 0 - 70c;v ddl = 2.5v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b v o = v dd *(0.5) 9 30 ? output impedance r dsn4b v o = v dd *(0.5) 9 30 ? output high voltage v oh4\b i oh = -5.5 ma 2 v output low voltage v ol4b i ol = 9.0 ma 0.4 v v oh @ min = 1.4 v -36 ma v oh @ max = 2.5 v -21 ma v ol @ min = 1.0 v 36 ma v ol @ max= 0.2 v 31 ma rise time t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 0.9 1.6 ns fall time t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.5 1.9 ns duty cycle d t4b v t = 1.25 v 45 50 55 % jitter tjcyc-cyc vt = 1.25 v 120 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b output low current i ol4b electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated.) parameter symbol conditions min typ max units output impedance r dsp3 v o = v d d *(0.5) 10 24 ? output impedance r dsn3 v o = v d d *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh @min= 2.0 v -54 ma v oh @ max=3.135 v -46 ma v ol @ min=1.0 v 54 ma v ol @ max=0.4 v 53 ma rise time t r3 v ol =0 .4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1 1.6 ns duty cycle d t3 v t = 1.5 v 45 50 55 % skew t sk3 v t = 1.5 v 50 250 ps jitter t jcyc-cyc v t = 1.5 v 140 250 ps 1 guaranteed by design, not 100% tested in production. output high current i oh3 i ol3 output low current
12 ics9248-99 0314c?09/18/03 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 v o = v d d *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max= 0.4 v 38 ma rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 2.5 ns fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.9 2.3 ns duty cycle d t1 v t = 1.5 v 45 50 55 % skew t sk1 v t = 1.5 v 390 500 ps jitter t jcyc-cyc v t = 1.5 v 110 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current i oh1 i ol1 electrical characteristics - ref1, 48mhz t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v v oh @min =1 v -29 ma v oh @max = 3.135 v -23 ma v ol @min =1.95 v 29 ma v ol @min=0.4 v 27 ma rise time t r5 v ol = 0.4 v, v oh = 2.4 v 1.948 4 ns fall time t f5 v oh = 2.4 v, v ol = 0.4 v 1.813 4 ns duty cycle d t5 v t = 1.5 v 45 52.6 55 % t j c y c-c y c v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc v t = 1.5 v; ref clocks 619 1000 ps 1 guaranteed by design, not 100% tested in production. jitter output high current i oh5 output low current i ol5
13 ics9248-99 0314c?09/18/03 l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 .d a0 2 7 .5 2 7 .0 3 7 .6 5 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ssop package ordering information ics9248 y f-99 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp

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